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| M62354P/FP/GP 8-bit 6ch D/A Converter with Buffer Amplifiers REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Description The M62354 is an integrated circuit semiconductor of CMOS structured with 6 channels of built-in D/A converters with output buffer operational amplifiers. The 3-wire serial interface method is used for the transfer format of digital data to allow connection with microcomputer with minimum wiring. It is able to cascading serial use with DO terminal. The output buffer operational amplifier operates in the whole voltage range from power supply to ground for both input/output. Features * 12-bit serial data input (3-wire serial data transfer method) * Highly stable output buffer operational amplifier allow operation in the all voltage range from power supply to ground. Application Adjustment/control of industrial or home-use electronic equipment, such as VTR camera, VTR set, TV, and CRT display. Block Diagram VCC 14 VDD 13 AO6 12 AO5 11 AO4 10 AO3 9 VSS 8 Buffer OP Amp + - + - + - D/A Ch6 5 D/A 4 D/A 8-bit R-2R segment D/A converter 3 L (6) ...... Address decoder L L L Ch1 2 D/A D11 10 9 8 D7 6 5 4 3 2 1 0 8-bit R-2R segment D/A converter + - 12-bit shift register + - + - 8-bit latch (6) .... 8-bit latch Buffer OP Amp 1 2 3 4 5 6 7 DO LD CLK DI AO1 AO2 GND REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Page 1 of 9 M62354P/FP/GP Pin Arrangement M62354P/FP DO LD CLK DI AO1 AO2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 M62354GP VCC VDD AO6 AO5 AO4 AO3 VSS DO LD CLK DI AO1 AO2 NC GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC VDD AO6 AO5 AO4 AO3 NC VSS NC: No connection (Top view) Outline: 14P4 PRSP0014DD-A (14P2N-A) (Top view) Outline: PLSP0016JA-A (16P2E-A) Pin Description Pin No. 4 (4) 1 (1) 3 (3) 2 (2) 5 (5) 6 (6) 9 (11) 10 (12) 11 (13) 12 (14) 14 (16) 7 (8) 13 (15) 8 (9) Note: Pin Name DI DO CLK LD AO1 AO2 AO3 AO4 AO5 AO6 VCC GND VDD VSS Function Serial data input terminal Serial data output terminal Serial clock input terminal LD terminal input high level then latch circuit data load 8-bit D/A converter output terminal Power supply terminal Digital and analog common GND D/A converter upper reference voltage input terminal D/A converter lower reference voltage input terminal ( ) : M62354GP REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Page 2 of 9 M62354P/FP/GP Block Diagram for Explanation of Terminals VCC 14 GND 7 DI 4 CLK 3 12-bit shift register D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 1 DO (8) (6) Address decoder 123456 2 LD D0 1 ..... 8-bit latch D7 D0 ............................... 6 ............................... ..... 8-bit latch D7 8-bit R-2R segment D/A converter 8-bit R-2R segment D/A converter + - + - ......................................... 13 5 12 8 AO1 VDD (VrefU) AO6 VSS (VrefL) Absolute Maximum Ratings Item Supply voltage D/A converter upper reference voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Symbol VCC VDD VIN VO Pd Topr Tstg Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 440 (P) / 250 (FP) / 150 (GP) -20 to +85 -40 to +125 Unit V V V V mW C C REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Page 3 of 9 M62354P/FP/GP Electrical Characteristics Item Supply voltage Circuit current Input leak current Input low voltage Input high voltage Output low voltage Output high voltage Symbol VCC ICC IILK VIL VIH VOL VOH Min 4.5 -- -10 -- 0.8 VCC -- VCC - 0.4 Limits Typ 5.0 0.7 -- -- -- -- -- Max 5.5 2.5 10 0.2 VCC -- 0.4 -- Unit V mA A V V V V Conditions CLK = 1 MHz operation VCC = 5 V, IAO = 0 A VIN = 0 to VCC IOL = 2.5 mA IOH = -400 A Item Current dissipation D/A converter upper reference voltage range D/A converter lower reference voltage range Buffer amplifier output voltage range Buffer amplifier output drive range Differential nonlinearity error Nonlinearity error Zero code error Full scale error Output capacitive load Buffer amplifier output impedance Symbol IDD VDD VSS VAO IAO SDL SL SZERO SFULL CO RO Min -- 3.5 Limits Typ 0.7 -- Max 1.3 VCC VCC - 3.5 VCC - 0.1 VCC - 0.2 1 1.0 1.5 2 2 0.1 -- Unit mA V Conditions VrefU = 5 V, VrefL = 0 V Data condition: at maximum current The output does not necessarily be the value within the reference voltage setting range. The output value is determined by the buffer amplifier output voltage range (VAO). IAO = 100 A IAO = 500 A Upper side saturation voltage = 0.3 V Lower side saturation voltage = 0.2 V VrefU = 4.79 V VrefL = 0.95 V VCC = 5.5 V (15 mV/LSB) Without load (IAO = 0 A) GND -- V 0.1 0.2 -1 -1.0 -1.5 -2 -2 -- -- -- -- -- -- -- -- -- -- 5 V mA LSB LSB LSB LSB F REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Page 4 of 9 M62354P/FP/GP AC Characteristics (VCC, VrefU = 5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = -20 to +85C, unless otherwise noted.) Item Clock "L" pulse width Clock "H" pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H" pulse width Data output delay time D/A output setting time Symbol tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDO tLDD Min 200 200 -- -- 30 60 200 100 100 70 -- Limits Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- 200 200 -- -- -- -- -- 350 300 Unit ns ns ns ns ns ns ns ns ns ns s Conditions CL 100 pF CL 100 pF, VAO: 0.5 4.5 V The time until the output becomes the final value of 1/2 LSB Timing Chart tCR tCKH tCF CLK tCKL DI tLDH tDCH tCHD tCHL tLDC LD tLDD D/A output tDO DO output REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Page 5 of 9 M62354P/FP/GP Digital Data Format Last LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 First MSB D11 DAC data DAC select data DAC Data D0 0 1 0 1 : 0 1 Note: D1 0 0 1 1 : 1 1 D2 0 0 0 0 : 1 1 D3 0 0 0 0 : 1 1 D4 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D6 0 0 0 0 : 1 1 D7 0 0 0 0 : 1 1 D/A Output (VrefU - VrefL) / 256 x 1 + VrefL (VrefU - VrefL) / 256 x 2 + VrefL (VrefU - VrefL) / 256 x 3 + VrefL (VrefU - VrefL) / 256 x 4 + VrefL : (VrefU - VrefL) / 256 x 255 + VrefL VrefU VrefU = VDD, VrefL = VSS DAC Select Data D8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC Selection Don't care AO1 selection AO2 selection AO3 selection AO4 selection AO5 selection AO6 selection Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Timing Chart (Model) MSB DI D11 D10 D9 D8 ............. LSB D2 D1 D0 CLK .................. LD D/A output REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Page 6 of 9 M62354P/FP/GP Typical Characteristics Upper Side Saturation Voltage vs. Output Source Current 150 150 Lower Side Saturation Voltage vs. Output Sink Current Upper Side Saturation Voltage VCC-VAOSATU (mV) Lower Side Saturation Voltage VAOSATL (mV) 0 200 400 600 800 1000 100 100 50 50 0 0 0 200 400 600 800 1000 Output Source Current IAOD (A) Output Sink Current IAOS (A) REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Page 7 of 9 M62354P/FP/GP Package Dimensions 14P4 EIAJ Package Code DIP14-P-300-2.54 JEDEC Code -- Weight(g) 1.0 Lead Material Alloy 42/Cu Alloy Plastic 14pin 300mil DIP 14 8 1 7 D Symbol A A1 A2 b b1 c D E e e1 L Dimension in Millimeters Min Nom Max 4.5 -- -- 0.51 -- -- 3.3 -- -- 0.4 0.5 0.6 1.4 1.5 1.8 0.22 0.27 0.34 19.0 19.2 18.8 6.15 6.3 6.45 2.54 -- -- 7.62 -- -- 3.0 -- 15 0 -- LA e b1 b JEITA Package Code P-SOP14-5.3x10.1-1.27 RENESAS Code PRSP0014DD-A Previous Code 14P2N-A MASS[Typ.] 0.2g 14 8 HE *1 E F A1 SEATING PLANE A2 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 Index mark *2 D A2 A1 Reference Symbol 7 c e1 Dimension in Millimeters E c D E A2 A1 A bp c HE e y L Detail F e y *3 bp Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0 8 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 A REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Page 8 of 9 L M62354P/FP/GP JEITA Package Code P-LSSOP16-4.4x5-0.65 RENESAS Code PLSP0016JA-A Previous Code 16P2E-A MASS[Typ.] 0.06g 16 9 HE E F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *1 1 Index mark 8 c A2 A1 Reference Dimension in Millimeters Symbol *2 D *3 e y bp Detail F D E A2 A A1 bp c HE e y L Nom Max 5.0 5.1 4.4 4.5 1.15 1.45 0 0.1 0.2 0.17 0.22 0.32 0.13 0.15 0.2 0 10 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7 Min 4.9 4.3 REJ03D0872-0300 Rev.3.00 Mar 25, 2008 Page 9 of 9 A L Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. 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Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. 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